The present invention relates to a non-volatile random-access memory (NVRAM) cell, more particularly to an NVRAM cell constituted by a volatile static type random-access memory (SRAM) cell portion and a non-volatile electrically erasable programmable read-only memory (EEPROM) cell portion.
Generally, in the art of a semiconductor memory device, an ideal semiconductor memory device has been awaited to be realized, wherein, the ideal semiconductor memory device is such that therein the data can be re-written without limitation, the access thereto can be made in a short time, and the type thereof is a non-volatile one.
Generally, an SRAM cell has a merit that the access time is short and the data can be re-written without limitation but a demerit that its type is a volatile one; on the contrary, an EEPROM cell has a merit that its type is a non-volatile one but a demerit that a long access time is required and the number of times for re-writing the data is limited.
To realize the ideal semiconductor memory device, recently, an NVRAM cell is developed by combining the merits of the SRAM cell and the EEPROM cell. When the power supply voltage of the NVRAM cell is ON, using the merit of the SRAM cell, the data can be written into or read out from the NVRAM cell in a short time and also the data can be re-written without any limitation. When the power supply voltage of the NVRAM cell is turned off, using the merit of the EEPROM cell, the data in the SRAM cell portion can be stored in the EEPROM cell portion and the data stored in the EEPROM cell portion can be recalled to the SRAM cell portion when the power supply voltage is turned on. The demerit of the long access time of the EEPROM cell gives no influence to the NVRAM cell because the data access is required only in a short time during the power supply voltage of the NVRAM cell is turned on and off.
However, the NVRAM cell has a problem that the size of it becomes large; accordingly, many trials have been made to reduce the cell size for increasing the packing density of the memory device consisting of the NVRAM cells. In the NVRAM cell, the SRAM cell portion therein consists of few components of a flip-flop circuit, so that the EEPROM cell portion therein becomes a subject for increasing the packing density of the NVRAM cell. The U.S. patent application Ser. No. 659,191 filed Oct. 9, 1984 and now U.S. Pat. No. 4,630,238 invented by the same inventor of the present invention gave a solution to the above problem by increasing the packing density of the EEPROM cell portion. According to the U.S. patent application Ser. No. 659,191 now U.S. Pat. No. 4,630,238, a prior art NVRAM cell was such as shown in FIG. 1 and an NVRAM cell embodying the patent application is such as shown in FIG. 2(a).
In FIGS. 1 or 2(a), the NVRAM cell functions as a memory matrix element of a memory device, wherein the element is designated by respective word line WL and respective pair of bit lines BL and BL of the memory device. The NVRAM cell of FIG. 1 consists of an SRAM cell portion 1 and an EEPROM cell portion 2 and the NVRAM cell of FIG. 2(a) consists of an SRAM cell portion 1 and an EEPROM cell portion 17; the SRAM cell portions 1 of FIGS. 1 and 2(a) are equal to each other. Compared between FIGS. 1 and 2(a), it can be seen that the improvement of the packing density of the NVRAM cell is performed by reducing the circuit components of the EEPROM cell portion 2. FIG. 2(b) shows a modified partial circuit of FIG. 2(a); i.e., in FIG. 2(b), instead of removing the capacitor C.sub.62 in FIG. 2(a), a control transistor Q.sub.100 is placed between the node N.sub.2 and the transistor Q.sub.61. The details of the function of the NVRAM cell in FIGS. 1 and 2(a) and of 2(b) are well discussed in the U.S. patent application Ser. No. 659,191 now U.S. Pat. No. 4,630,238, so that the explanation of these details are not repeated here.
In the U.S. patent application Ser. No. 659,191 now U.S. Pat. No. 4,630,238, many embodiments were disclosed, and above all it becomes practically cleared that the NVRAM cell shown in FIG. 2(a) is most useful, because, as seen from FIG. 2(a), the NVRAM cell of FIG. 2(a) has the structure of removing the connection between the node N.sub.1 of the SRAM cell portion 1 and the circuit of the EEPROM cell portion 2, so that the NVRAM cell of FIG. 2(a) is effective not only for increasing the packing density of the NVRAM cell but also for obtaining the freedom for designing the structure of the NVRAM cell. However, as shown in FIG. 2(a), the EEPROM cell portion 17 operates with two kinds of the power sources V.sub.H1 and V.sub.H2. The two kinds of power sources make the peripheral circuit of the NVRAM cell a little more complicate, which, however, is not so negative factor for the NVRAM cell of FIG. 2(a). The two kinds of power supply voltage bring new problems to the NVRAM cell of FIG. 2(a) as follows.
(1) Two steps such as "pre-set" and "set" are necessary every time the floating gate FG.sub.62 of the transistor Q.sub.61 in the EEPROM cell portion 17 is charged or discharged for storing the data, so that it takes too much time to store the data.
(2) When the memory device consisting of a plurality of the NVRAM cells is used as a read only memory (ROM) device, the two steps of "pre-set" and "set" must be functioned every time the data is stored and recalled; accordingly, the life of the memory device is reduced. And,
(3) in a semiconductor device, a PN junction generally produces the leakage current, e.g., the leakage current flows at a node N.sub.3 in FIG. 2(a), so that the holding time, which should be long for the NVRAM cell, of the capacitance-coupling-charge becomes short when the temperature at the PN junction increases. Therefore, repeating the charging on the floating gate again and again is necessary for lengthening the apparent holding time under the consideration of the upper allowable limit of the temperature characteristic of the NVRAM cell. However, the repeat of the charging cannot be made in the NVRAM cell of FIG. 2(a), because the floating gate FG.sub.62 is always discharged every time the new data is going to be stored in the EEPROM cell portion 17.